INTENSET

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Interpret as INTENSET

SSDEN=DISABLED, MSTIDLEEN=DISABLED, SSAEN=DISABLED

Description

SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Fields

SSAEN	Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. 0 (DISABLED): Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 1 (ENABLED): Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
SSDEN	Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. 0 (DISABLED): Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. 1 (ENABLED): Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
MSTIDLEEN	Master idle interrupt enable. 0 (DISABLED): No interrupt will be generated when the SPI master function is idle. 1 (ENABLED): An interrupt will be generated when the SPI master function is fully idle.

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